1. Field of the Invention
The present invention is generally related to the synchronization protocol between a floating point unit (FPU) and a fixed point unit (FXU) during data load operations. More particularly, this synchronization allows out of order load operations when a data cache miss occurs, thereby improving performance of the system.
2. Description of Related Art
Currently it is known to couple a FXU and FPU such that the fixed point unit can operate as the control unit for the floating point load and store operations, "IBM RISC System/6000 Technology", First Edition, published. 1990, (hereby incorporated by reference) pgs. 24-30. For example, in the IBM RISC system/6000 workstations (RISC System/6000 is a trademark of IBM Corp.) the FXU is used as an address generator for the FPU such that data from the data cache unit (DCU) is loaded into the FPU only when addressed by the FXU. A problem exists since the FPU and FXU operate in a synchronous manner and when a data cache miss occurs, several cycles may elapse before the data can be loaded into the FPU. Thus, an inefficiency exists since the FPU is sitting idle for several machine cycles.
U.S. Pat. No. 4,961,162, hereby incorporated by reference, describes using a fixed point processor to compute a memory address for the floating point data required for floating point operations. U.S. Pat. No. 4,763,294 is another example of the prior art wherein a floating point unit is coupled to a central processing unit and is capable of executing floating point instructions while the CPU executes some non-floating point operations in parallel. However, it can be seen that only a single data port is provided to the FPU and any data load misses will cause the FPU to sit idle for however many machine cycles it takes to correct the data miss. U.S. Pat. No. 5,150,470 is an instruction execution circuit that tags decoded instructions for execution when corresponding data becomes available. U.S. Pat. No. 5,075,840, hereby incorporated by reference, describes a buffer which stores instructions for execution by two processors. IBM Technical Disclosure Bulletin, vol. 32, no. 12, May 1990, pgs. 132-133 discloses that a synchronization pulse is sent from a fixed point unit to an instruction cache unit and describes a method of predicting translation errors for words being loaded or stored.
IBM Technical Disclosure Bulletin, vol. 35, no. 1B, June, 1992, pg. 398-399 describes coordinating and controlling instruction execution in fixed point and floating point instructions with relation to a fixed point instruction. This counter allows the floating point unit to complete an instruction only when the counter has a number greater than zero so that an executed floating point instruction will never get backed out. However, there is no description of more than a single data port between the cache unit and the floating point unit.
It can readily be seen that a processor system that allows virtually continuous execution of instructions on the floating point unit, regardless of the existence of a data load miss, would be desirable.